Employing heterogeneity in multi-core processor design has been demonstrated to be an effective approach toward power efficient computing. By integrating different types of cores in a single chip, a heterogeneous multi-core processor can provide the architectural capability to accommodate diverse computational requirements of a program. It achieves efficient computing by running the program on the core that can be most suitable for its execution in terms of energy delay product (EDP).
While the heterogeneous multi-core system provides the architectural support to match the programs' diverse resource requirements, it can be the program scheduling mechanism that leverages this architecture opportunity to provide energy efficient computing. A program scheduling mechanism that considers power and performance can be helpful in efficiently parsing programs to the multi-core processor.
Prior research on program scheduling in heterogeneous systems mainly focused on scheduling the subtasks of the programs in order to minimize the overall subtask execution time. This execution time driven scheduling mechanism is not as desirable in modern heterogeneous multi-core processors since power consumption, in addition to the performance, has become a consideration in designing a scheduling algorithm.
Therefore, systems and methods are desired for efficiently utilizing multi-core processors in executing applications that overcome challenges in the art, some of which are described above.